Multi-rate analog-to-digital converter

ABSTRACT

A Multi-Rate Analog-to-Digital Converter ( 19 ) is coupled to a single crystal oscillator ( 17 ) as a reference clock and has at least two separate channels arranged to sample and convert input data at two differing clock rates. Each channel derives a clock signal from the reference clock. Associated with each of the channels is a Sigma-Delta converter ( 10   a   , 10   b ) comprising a modulator ( 12 ), a filter ( 14 ) and a resampler ( 18 ). The modulator ( 12 ) receives input data and provides a data signal to the filter ( 14 ), which itself provides a filtered data signal to the associated data resampler. The data resampler resamples the data and provides a digital output signal. As there is sampling in the digital domain the advantages associated with signal processing, speed and low noise injection are obtained. Similarly as the output of the modulator ( 12 ) is in digital form, it can be manipulated and processed readily and with the existing software.

BACKGROUND OF THE INVENTION

This invention re lates generally to Analog to Digital Converters(ADC's) and more particularly to Multi-Rate ADC's.

Analog to Digital Converters (ADC's) are used in a myriad electronicdevices. An example of one type of device that incorporates an ADC is amulti-mode receiver. A multi-mode receiver is used in telecommunicationequipment such as a mobile telephone or digital tuner.

Multimode receivers use crystal oscillators to generate a single outputfrequency referred to as a clock frequency. Different carrier signalsrequire different clock frequencies in order to demodulate them. Theclock frequencies and other protocols vary according to differentstandards. For example, the GSM standard requires cocks to operate at270.833 kHz or at multiples thereof, whereas Wideband Coded DivisionalMultiplexed Access standard (WCDMA) operates at 3.84 MHz or multiplesthereof. Because there is no direct way of deriving one frequency fromanother, multi-mode devices, operating at different standards, need tohave separate clocks capable of generating different clock referencefrequencies. So called multi-clock arrangements are not only expensive,but also add size and complexity to portable devices, such as mobiletelephones.

Increasingly, because demands placed upon channel carrying capacity arebecoming more exacting the requirements imposed by internationalTelecommunication Standards on such features as sensitivity level, arealso becoming more stringent. Another drawback of such multi clockarrangements is that there is an increased risk of cross-talk andfrequency mixing. When this occurs an intolerable amount of noise may beintroduced into a system, to such a degree, that the performance of theADC may not meet the Signal to Noise Ratio (SNR) and noise floor levelsand may not allow telephones to meet the sensitivity levels demanded bysome of the standards.

PRIOR ART

A solution to this problem has been to use a crystal reference and aphase locked loop (PLL) capable of generating frequencies across a broadspectrum. However, these not only add complexity, but also increase thesize of the circuits or radios. Furthermore when the frequencies arehigh, there is a risk that they mix together due to parasitic coupling.This is highly undesirable because a large spectrum of frequencies isinherent in a clocked square wave, it is likely that some harmonicfrequencies which are generated will interfere one with another.

An article of relevance is entitled “Sample Rate Conversion for SoftwareRadio” and was published in IEEE Communications Magazine in August 2000,by T. Hentschel and M. Akune. The article describes a fractional SampleRate Converter (SRC) for a software definable radio, with examplessupporting GSM, IS-95 and UMTS. This fractional SRC allowsanalog-to-digital conversion to be done at a fixed clock rate fordifferent communication standards, because a conversion to the samplerate, dedicated to each communication standard, is operated by software.However, this fractional sample rate conversion requires using bothinterpolation and decimation functions.

A partial solution is described in U.S. Pat. No. 5,856,796 (SONY), whichdescribes a method of sample rate conversion using interpolators anddecimators. The method is particularly applicable for audio sampling.

Another solution has been proposed for high quality audio signalprocessing and conversion as its main objective. It is disclosed in U.S.Pat. No. 5,880,980 (ROCKWELL CORPORATION). A distributed decimation isdescribed, which ends with a sample rate conversion. This techniqueallows the conversion rate in the final sample rate converter to belimited to a range between 1 and 2 thus, saving memory.

The aforementioned solutions are effective. However, no advantage istaken to reduce the processing requirements of components such asoscillators or phase locked loops (PLL's). Furthermore there is noteaching provided which overcomes the problem associated with operatingusing two different reference clocks. A reason for this may be thatimplementation of some of these alternatives are not alwaysstraightforward. For example a single crystal oscillator, in conjunctionwith a phase locked loop (PLL) has the disadvantage of introducinganalog signals, with associated noise problems. Moreover, these proposedtechniques require using both interpolators and decimators whichrepresents a significant increase in of signal processing and cost.

An object of the present invention is to solve the aforementionedproblems, by providing an improved Multi-Rate Analog-to-DigitalConverter (MRADC).

SUMMARY OF THE INVENTION

According to the present invention there is provided a Multi-RateAnalog-to-Digital Converter coupled to a single crystal oscillator as areference clock and having at least two separate channels arranged tosample a nd convert in put data at two differing clock rates, eachchannel deriving a clock signal from said reference clock; associatedwith each of the channels is a Sigma-Delta converter the Sigma-Deltaconverter comprises a Sigma-Delta modulator, a filter and a resampler;the Sigma-Delta modulator receives input data and provides a data signalto the filter, which itself provides a filtered data signal to theassociated data resampler; the data resampler resamples the data andprovides a digital output signal.

Advantageously re-sampling is controlled by an output signal of a clocksynthesizer, deriving an appropriate clock rate from the referenceclock, or an integer sub-multiple of the reference clock by means of aphase accumulator coupled to a comparator.

Preferably the frequency of the reference clock is an integer multipleof the maximum rate at which the Sigma-Delta converter operates.

Where there are two or more channels, the conversion performed in eachchannel, may be simultaneous or time multiplexed.

As there is sampling in the digital domain the advantages associatedwith signal processing, speed and low noise injection are obtained.Similarly as the output of the Sigma-Delta modulator is in digital form,it may be manipulated and processed readily and with existing software.Furthermore as Sigma-Delta modulators tend to oversample: that is theytend to sample at frequencies in excess of the Nyquist rate;configuration of the decimators is relatively straightforward and thisgreatly eases post processing of the Sigma-Delta modulator outputsignal. An advantage of this is that there is no longer a requirement toinclude an additional PLL for each mode of a multi-mode receiver.

Preferably the frequencies at each of the desired rates at which data issampled are integer multiples of the highest standard frequency rate ofthe signals to be converted. For example, in a MRADC having to convertboth WCDMA and GSM signals, considering that the so-called 1× rate foreach of these standards is 3.84 MHz and 270.833 kHz respectively, datais sampled at integer multiples of the 3.84 MHz rate in each of thechannels. For example, the sampling rate could be 15.36 MHz (4×-WCDMArate), 30.72 MHz (8×-WCDMA rate) or 46.08 MHz (12×-WCDMA rate) in theSigma-Delta modulator.

Preferably the frequencies at each of the desired rates at which data isresampled at the last stage of the decimator is an integer multiple ofthe so-called 1× rate for each of the standard signals to be convertedby its respective channel. For example, data could be resampled at 15.36MHz (4×-WCDMA rate) in the channel handling WCDMA signals while datacould be resampled at 541.667 kHz (2×-GSM rate) or 270.833 kHz (1×-GSMrate) in the channel handling GSM signals. Provided the ratio betweenthe sampling rate of the Sigma-Delta modulator and the 1×rate of thestandard signal converted by each channel is sufficiently large(typically larger than 8), then any quantisation noise occurring in theSigma-Delta modulator is kept to a minimum in the desired signal band.Decimation is then advantageously carried out between the data source,that is the Sigma-Delta modulator output, and the data sink, namely theoutput of the resampler. The decimation process provides low passfiltering which may remove as much as needed of any out-of-band noise,such that harmonics of square wave signals re-sampling the output signalat the desired output rate, will only remove or fold a negligiblecontribution of the out-of-band noise in the desired signal band at thetime re-sampling is done.

A regenerator can be arranged to recycle at a sub-multiple of thereference clock frequency the data in the resampler. The recycling maybe done at an integer sub-multiple or at a fractional sub-multiple ofthe reference lock frequency.

The regenerator is a digital clock synthesizer comprising: a phaseaccumulator and a comparator. Accuracy of the resampling signalfrequency is determined by the number of bits (q) used for accumulatingthe phase value of the resampling signal. The phase accumulator isactivated by the reference clock or by an integer sub-multiple of thereference clock. The frequency of the resampling signal (f_(x)) isdetermined by the number of bits (q), by the frequency (f_(ref)/α) ofthe clock activating the phase accumulator and by the phase increment(p) added at each period of the activating dock according to the wellknown following function:f _(x)=(p/2^(q))·f_(ref)/α

If q is large enough then it is possible to obtain a high degree ofaccuracy in generating the resampling signal in the relevant mode.

Sample rate conversion (SRC) can impose significant demands upon aDigital Signal Processor (DSP) because interpolators and decimators areemployed. However, inclusion of a low pass filter (LPF) in anySigma-Delta converter enables decimation. As a result of theoversampling and quantisation noise shaping that occur in the modulator,decimation drastically attenuates the noise components that may fallinto the desired signal band after resampling. The inventors haverealised that this feature may be employed to improve the noise floorlevels of a Multi-Rate Analog-to-Digital Converter as well as reduce anyallasing that may occur.

By including a low pass filter (LPF) at the output of the, or each,Sigma-Delta modulator, a lower sampling rate can be achieved at there-sampler, for example from a system clock frequency of 30.72 MHz to achoice of lower frequencies. The clock synthesiser is coupled to aclocked control switch and advantageously is able to vary the rates atwhich clocking occurs. Effectively therefore a variable frequency clockis achievable. Typically the clock rate is 270.833 kHz or 541.666 kHzfor the GSM channel.

According to another aspect of the invention there is provided a methodof Analog-to-Digital Conversion comprising the following steps: derivinga reference clock frequency suitable for input to at least two separatechannels at two differing clock rates, each channel is arranged, in use,to sample and convert input data at the two differing clock rates;deriving a clock signal from said reference lock; modulating data ineach channel using a Sigma-Delta modulator; receiving input data fromthe Sigma-Delta modulator, low pass filtering the data signal so as toprovide a data signal to an associated data re-sampler, said re-samplerre-samples the data thereby providing a digital converted outputResampling the signal at a rate close to or equal to the 1× rate of thestandard signal in each channel avoids the need for introducing a nowhigh frequency reference clock and associated problems of harmonicinterference between several high frequency reference docks. Preferredembodiments of the invention will now be described, by way of examplesonly, and with reference to the Figures in which:

BRIEF DESCRIPTION OF FIGURES

FIG. 1 is a simplified block diagram of a clock synthesizer;

FIG. 2 is a block diagram of a preferred embodiment of the invention;

FIG. 3 is a graph showing output from the Sigma-Delta modulator at8×-WCDMA clock rate;

FIG. 4 is a graph showing the output from the low pass filter at8×-WCDMA rate; and

FIG. 5 is a graph showing the output of the MRADC after resampling thesignal at 2×-GSM clock rate.

DETAILED DESCRIPTION OF THE INVENTION

Referring to the Figures, FIG. 1 shows a diagrammatical representationof a Clock Synthesizer 16. The input parameter, p, is selected accordingto the main clock (not shown) frequency, f_(ref)/α, the output frequencyto generate, f_(x), and the number of bits, q, used to accumulate thephase of the output dock signal. A register 20 receives an input fromadder 26 and is activated by an input clock which is an integersub-multiple of the reference clock (not shown). Alternatively theregister could be clocked by the reference clock itself. Consequently,the frequency of the clock activating register 20 is given by f_(ref)/α,where a is an integer number larger or equal to 1. Register 20 is partof a closed loop also comprising the adder 26. The closed loopaccumulates a phase count by means of an increment, p, added to anotherinput of the adder 26. The register 20 presents its output 28 to aComparator 30. Comparator 30 compares output from register 20 with avalue derived from 2^(q−1). Output 32 from the comparator 30 istherefore in the form of a digitally synthesised clock whose frequencyis given by.f _(x)=(p/2^(q))·f_(ref)/α

FIG. 2 shows a Multi-Rate Analog-to Digital converter 19 comprising twoSigma-Delta converters 10 a and 10 b. A reference clock generator 17provides an output signal called the single reference clock. For examplethe frequency of this clock may be 30.72 MHz, which is the 8×-WCDMArate. Each Sigma-Delta converter 10 a and 10 b is configured to operateat a different frequency channel. Each frequency can support aparticular standard. In a particularly preferred embodiment converter 10a handles a WCDMA signal and converter 10 b handles a GSM signal. In ageneral case, each Sigma-Delta converter comprises a clock divider 9, aSigma-Delta modulator 12, a Low Pass Filter 14, a Clock Synthesizer 16and a re-sampling switch 18.

In the particular case of the above example, shown in FIG. 2, clockdivider 9 a is reduced to a bypass connection as reference clock isdirectly applied to Sigma-Delta modulator 12 a; while clock divider 9 bachieves a frequency division by a factor of 2. This is equivalent toallowing parameter N to equal 1 and parameter M to equal 2.

Therefore Sigma-Delta modulator 12 over samples and quantises each inputsignal, producing a digital output at the sampling rate relative to eachchannel. The digital output of the Sigma-Delta modulator 12 is afunction of the input signal and of the quantisation noise.

The signal at the output of the Sigma-Delta modulator 12 is filtered byLow Pass Filter 14. Thus, most of any out-of-band noise components aredrastically attenuated.

Clock synthesizer 16 is clocked by a reference clock 17 after it hasbeen divided by the appropriate integer factor for each channel. ClockSynthesizer 16 delivers a control signal to the switch 18. In the firstSigma-Delta converter 10 a the first analog input signal may for examplebe sampled at the 8×-WCDMA rate of 30.72 MHz in the modulator 12 a andmay then be decimated by a factor 2, down to the 4×-WCDMA rate of 15.76MHz by a low pass filter (LPF) 14 a, the Clock Synthesizer 16 a and there-sampling switch 18 a. The output signal from clocked switch 18 a Isthen suitable for handling WCDMA signals.

In the second Sigma-Delta converter 10 b the second analog input signalmay for, example, be sampled at the 4×-WCDMA rate of 15.36 MHz in themodulator 12 b and may then be decimated down to the 2×-GSM rate of541.667 kHz by means of LPF 14 b, Clock Synthesizer 16 b and there-sampling switch 18 b. The output signal from clocked switch 18 b Isthen suitable for handling GSM signals.

In the example given for converter 10 a the signal at the output of theSigma-Delta modulator only needs to be decimated by a factor of 2. ClockSynthesizer 16 a may then be reduced to a simple frequency divider by afactor of 2, which is well known from those skilled in this art.Nevertheless, the signal at the output of Sigma-Delta Modulator 12 bneeds to be decimated by a non-integer factor and this requires ClockSynthesizer 16 b to be realised by means of an arrangement such asdescribed in FIG. 1.

FIG. 3 shows the frequency spectrum of the signal at the output of theSigma-Delta Modulator 12 b using the above example circuit of FIG. 2.The sampling rate at this point is 15.36 MHz and the horizontal scale isexpressed relative to this frequency. The frequency range extends to1.536 MHz. For the sake of simplicity, the second analog input signal isa 2-tone signal instead of the regular GMSK-modulated signal in use inthe GSM standard. Therefore, at the output of the Sigma-Delta Modulator,these two tones may be noticed on the left-hand side of the spectrumcorresponding to low frequencies while most of the quantisation noiseproduced by the Sigma-Delta modulation loop may be observed at upperfrequencies.

FIG. 4 shows the frequency spectrum of the signal at the output of theLow Pass Filter 14 b. The horizontal scale still relates to the samplingrate of 15.36 MHz. The two low frequency tones have not been modifiedbut most of the high frequency noise has been significantly attenuated.

FIG. 5 shows the frequency spectrum of the signal at the output of there-sampling switch 18 b. Here, the signal has been resampled at 541.667kHz. Thus, the horizontal scale spans up to 0.5×541.667 kHz=270.833 kHz.The two low frequency tones have not been modified. The noise levelpresents a shaping which is typical of a low frequency portion producedby a Sigma-Delta modulation loop. This indicates that the amount of highfrequency noise, which has been aliased by interference with theharmonics of the re-sampling dock signal, is negligible. The attenuationprovided by Low Pass Filter 14 is sufficient to achieve this goal.

The Multi-Rate Analog-to-Digital Converter of FIG. 2 may be extended tomore than two channels by adding further Sigma-Delta converters 10 a and10 b. Furthermore, as this arrangement does not require the decimatingfactor to be an integer, it may be seen that many different sorts ofsignals can be supported in addition to or instead of WCDMA and GSM.Appropriate parameters need to be set in the Clock Synthesizer in orderto allow proper decimation between the clock rate at the output of theSigma-Delta Modulator and the clock rate after re-sampling.Additionally, the sampling rate in the Sigma-Delta Modulator and there-sampling rate may be adapted to each standard in order to providesufficient over sampling and to allow for efficient quantisation noiseshaping in the modulator and effective attenuation of out-of-band noisecomponents in the Low Pass Filter.

The over-sampling ratio between both clock rates is related to theamount of noise aliased in the signal band by the re-sampling operationdue to the harmonics of the re-sampling square wave signal. Knowing thisover sampling ratio and the amount of in-band acceptable noise at thecorresponding Sigma-Delta converter output, the efficiency of the LowPass Filter must be adjusted accordingly.

Table 1 shows a range of different desired output rates and how toobtain these in the particular case of using a single reference clockrate of 30.72 MHz

Sampling rate in Phase Number of Single Sigma- increment phase bits ‘q’Re- reference Delta ‘p’ in Clock in Clock sampling Equivalent Supportedclock Modulator Synthesizer Synthesizer frequency rate signals 30.7230.72 — — 15.36 8x- WCDMA MHz MHz MHz WCDMA 30.72 30.72 4′469′555 262.046 2x-GPS GPS MHz MHz MHz 30.72 15.36 2′366′578 26 541.667 2x-GSM GSMMHz MHz kHz 30.72 3.84 MHz 1′698′693 26 97.2 kHz 2x-IS136 IS136 MHz

In the cases where different sorts of signals do not need to beprocessed simultaneously but during dedicated periods of time, theSigma-Delta converters 10 a and 10 b In FIG. 2 do not need to bephysically implemented. A single Sigma Delta Converter could beimplemented and multiplexed over time with different sets of parametersrelated to each of the signals to be handled. This, as well asre-configuration of the standards, may be achieved by and under controlof dedicated software.

The invention has been described by way of example only and it will beappreciated that variation may be made to the embodiments described,without departing from the scope of the invention.

1. A Multi-Rate Analog-to-Digital Converter coupled to a single crystaloscillator as a reference clock, said Multi-Rate Analog-to-DigitalConverter comprising: at least two separate channels arranged to sampleand convert input data at two differing clock rates, each channelderiving a clock signal from said reference clock, wherein each of thechannels includes a Sigma-Delta converter, the Sigma-Delta converterincluding a Sigma-Delta modulator, a filter and a data resampler whereinthe Sigma-Delta modulator receives input data and provides a data signalto the filter, wherein the filter provides a filtered data signal to theassociated data resampler, and wherein the data resampler resamples thedata and provides a digital output signal.
 2. The Multi-RateAnalog-to-Digital Converter (MRADC) according to claim 1, wherein thefilter in the Sigma-Delta converter is a decimation filter.
 3. TheMulti-Rate Analog-to-Digital Converter (MRADC) according claim 2 whereinthe decimation filter is a low pass filter.
 4. The Multi-RateAnalog-to-Digital Converter (MRADC) according to claim 2, whereinsigma-delta modulation and decimation only are carried out between adata source and a data sink.
 5. The Multi-Rate Analog-to-DigitalConverter (MRADC) according to claim 1, wherein a regenerator isarranged to recycle signals at an integer sub-multiple of the referenceclock frequency.
 6. The Multi-Rate Analog-to-Digital Converter (MRADC)according to claim 5, wherein a regenerator is arranged to produce aresampling clock signal from the reference clock signal by means of aphase accumulator and a comparator.
 7. The Multi-Rate Analog-to-DigitalConverter (MRADC) according to claim 6, wherein the frequency accuracyof the re-sampling clock determines the number of bits (q) used toexpress the phase of the resampling clock in the regenerator.
 8. TheMulti-Rate Analog-to-Digital Converter (MRADC) according to claim 6,wherein the frequency (f_(x)) of the resampling clock is determined bythe phase increment (p) added at every period of the sampling clock, thesampling clock frequency (f_(ref)/α) and the number of bits (q) used toexpress the phase of the resampling clock.
 9. The Multi-RateAnalog-to-Digital Converter (MRADC) according to claim 5, wherein aregenerator is arranged to produce a resampling clock signal from aninteger sub-multiple of the reference clock by means of a phaseaccumulator and a comparator.
 10. The Multi-Rate Analog-to-DigitalConverter (MRADC) according to claim 9, wherein a regenerator ifarranged to produce a resampling clock signal from an integersub-multiple of the reference clock by means of a phase accumulator anda comparator.
 11. The Multi-Rate Analog-to-Digital Converter (MRADC)according to claim 9, wherein the frequency accuracy of the re-samplingclock determines the number of bits (q) used to express the phase of theresampling clock in the regenerator.
 12. The Multi-RateAnalog-to-Digital Converter (MRADC) according claim 5, wherein aregenerator is arranged to recycle signals at a fractional sub-multiplefrequency of the reference clock frequency.
 13. The Multi-RateAnalog-to-Digital Converter (MRADC) according to claim 1, wherein theSigma-Delta converter comprises a Sigma-Delta modulator and a pluralityof successive decimation filters.
 14. The Multi-Rate Analog-to-DigitalConverter (MRADC) according to claim 1, wherein the at least twoseparate channels include using a single Sigma-Delta converter is usedand is adapted to be operated upon first and second signals in a timemultiplexed manner, so as to convert first and second input signals atdifferent sampling rates.
 15. The Multi-Rate Analog-to-Digital Converter(MRADC) according to claim 1, wherein data at the input of at least onechannel is sampled at the reference clock rate.
 16. The Multi-RateAnalog-to-Digital Converter (MRADC) according to claim 1, wherein thedata at the input of at least one channel is sampled at an integersub-multiple of the reference clock.
 17. The Multi-RateAnalog-to-Digital Converter (MRADC) according to claim 1, wherein atleast one Sigma-Delta converter is arranged to sample data at frequencyof 46.08 MHz.
 18. The Multi-Rate Analog-to-Digital Converter (MRADC)according to claim 1, wherein at least one Sigma-Delta converter isarranged to sample data at frequency of 30.72 MHz.
 19. The Multi-RateAnalog-to-Digital Converter (MRADC) according to claim 1, wherein atleast one Sigma-Delta converter is arranged to sample data at frequencyof 15.36 MHz.
 20. A method of Analog-to-Digital Conversion comprising:deriving a reference clock frequency suitable for input to at least twoseparate channels at two differing clock rates, each channel isarranged, in use, to sample and convert input data at the two differingclock rates; deriving a clock signal from said reference clock;modulating data in each channel using a Sigma-Delta modulator; receivinginput data from the Sigma-Delta modulator; low pass filtering the datasignal so as to provide a data signal to an associated data re-sampler,said re-sampler re-samples the data thereby providing a digitalconverted output.